This invention relates to programmable logic device (“PLD”) integrated circuits and other devices of that general type (all referred to generically herein as PLDs). More particularly, the invention relates to certain aspects of the organization (“architecture”) of the circuitry of a PLD, and to methods for implementing a user's logic design in such PLD architectures.
PLDs are known that have logic elements (“LEs”) grouped in clusters that are sometimes referred to as logic array blocks or LABs. An example of this type of PLD architecture is shown in Cliff et al. U.S. Pat. No. 5,260,611. In this type of architecture, each LE has a local feedback connection from its output to inputs of all the logic elements in the LAB that includes that LE. Each LE can also output to the general interconnection resources of the PLD. Each LE can get its inputs from the associated local feedback connections and/or from the general interconnection resources.
Dedicated local feedback connections have a number of advantages such as speed. However, they do consume substantial resources of the PLD (e.g., space on the PLD). More efficient PLD architectures are always being sought.